In many image processing devices such as a system LSI mounted on an imaging device such as a still image camera, a moving image camera, a medical endoscope camera, or an industrial endoscope camera, one connected dynamic random access memory (DRAM) is shared by a plurality of built-in processing blocks. In such a system LSI, the plurality of built-in processing blocks are connected to a data bus inside the system LSI, and each processing block accesses the DRAM in direct memory access (DMA).
Also, there are processing blocks that include a plurality of processing modules and perform pipeline processing by the processing modules being connected in series among the processing blocks provided in such a system LSI. For example, in a system LSI provided in an imaging device, an image processing section that performs image processing is a processing block that performs pipeline processing. In addition, the image processing section implements high-speed image processing in the image processing section according to pipeline processing in which a plurality of image processing modules that perform image processing are connected in series. Generally, a data buffer which delivers data between the processing modules is provided in a processing block having a plurality of processing modules configured to perform the pipeline processing, a delay of processing in each processing module is absorbed by the data buffer and the pipeline processing can be performed normally.
For example, Japanese Unexamined Patent Application, First Publication No. H10-334225 discloses technology of an image processing device having a pipeline configuration in which a double buffer, which is a data buffer, is provided between processing stages which are processing modules. In the image processing device disclosed in Japanese Unexamined Patent Application, First Publication No. H10-334225, the pipeline processing in which processing by each processing stages is sequentially performed, by delivering data between the processing stages via the double buffer is implemented.
In the image processing device disclosed in Japanese Unexamined Patent Application, First Publication No. H10-334225, data processed by a previous processing stage is temporarily stored in the double buffer and the data stored in the double buffer is read by a subsequent processing stage, so that the data is delivered from the previous processing stage to the subsequent processing stage. That is, in the image processing device disclosed in Japanese Unexamined Patent Application, First Publication No. H10-334225, when data is delivered from the previous processing stage to the subsequent processing stage, writing of data to the double buffer by the previous processing stage and reading of data from the double buffer by the subsequent processing stage are necessarily performed.